The present invention relates to a semiconductor devices and fabrication methods thereof. More specifically, the present invention relates to a semiconductor device having a capacitor and a contact plug in a DRAM (Dynamic Random Access Memory) or the like, and to a manufacturing method thereof. The present invention also relates to MIM capacitor fabrication methods and systems. The present invention also relates to logic-based embedded DRAM devices and manufacturing methods thereof.
In the integrated circuit (IC) industry, manufacturers are currently imbedding dynamic random access memory (DRAM) arrays on the same substrate as CPU cores or other logic devices. This technology is being referred to as embedded DRAM (eDRAM). Embedded DRAM generally can provide micro controller (MCU) and other embedded controllers faster access to larger capacities of on-chip memory at a lower cost than that currently available using conventional embedded static random access memory (SRAM) and/or electrically erasable programmable read only memory (EEPROM).
A semiconductor memory, such as a DRAM or embedded DRAM, mainly consists of a transistor and a capacitor. Therefore, improvement in the efficiency of these two structures tends to be the direction in which technology is developing. DRAM is generally a volatile memory, and the way to store digital signals is decided by charge or discharge of the capacitor in the DRAM. When the power applied on the DRAM is turned off, the data stored in the memory cell completely disappears. A typical DRAM cell usually includes at least one field effect transistor (FET) and one capacitor. The capacitor is used to store the signals in the cell of DRAM. If more charges can be stored in the capacitor, the capacitor has less interference when the amplifier senses the data. In recent years, the memory cell of a DRAM has been miniaturized more and more from generation to generation. Even if the memory cell is minimized, a specific charge is essentially stored in the storage capacitor of the cell to store the information.
When the semiconductor enters the deep sub-micron process, the size of the device becomes smaller. For the conventional DRAM structure, this means that the space used by the capacitor becomes smaller. Since computer software is gradually becoming huge, even more memory capacity is required. In the case where it is necessary to have a smaller size with an increased capacity, the conventional method of fabricating the DRAM capacitor needs to change in order to fulfill the requirements of the trend.
There are two approaches at present for reducing the size of the capacitor while increasing its memory capacity. One way is to select a high-dielectric material, and the other is to increase the surface area of the capacitor.
There are two main types of capacitor that increase capacitor area. These are the deep trench-type and the stacked-type, where digging out a trench and filling the trench with a conductive layer, a capacitive dielectric layer and a conductive layer in sequence for the capacitor form the deep trench-type capacitor.
When a dielectric material with a relatively high dielectric constant is used in a stacked capacitor, the materials for manufacturing the upper and the bottom electrodes need to be gradually replaced in order to enhance the performance of the capacitor. A structure known as a metal-insulator-metal (MIM) structure possesses a low-interfacial reaction specificity to enhance the performance of the capacitor. Therefore, it has become an important topic of research for the semiconductor capacitor in the future.
Cell areas are reduced, as a semiconductor device needs ultra-high integrity. Thus, many studies for increasing the capacitance of a capacitor are being developed. There are various ways of increasing the capacitance such as forming a stacked or trench typed three-dimensional structure, whereby a surface area of a dielectric layer is increased.
In order to constitute a cell area in a DRAM fabrication, transistors and the like are formed on a semiconductor substrate, storage and plate electrodes of polycrystalline silicon and a dielectric layer are formed wherein the dielectric layer lies between the electrodes, and metal wires are formed to connect the devices one another.
The obtainable capacitance of the storage capacitor tends to decrease dependent upon the level of the miniaturization of the storage cell. On the other hand, the necessary capacitance of the capacitor is almost constant when the storing voltage to be applied across the capacitor is fixed. Therefore, it is necessary for the capacitor to compensate the capacitance decrease due to the miniaturization by, for example, increasing the surface area of the capacitor. This surface area increase has been popularly realized by increasing the thickness of the lower electrode (or, storage electrode) of the capacitor. A typical capacitor utilized in DRAM fabrication is the Metal Insulator Metal (MIM) capacitor, which is usually located in the memory region of DRAM and embedded DRAM to increase the capacitance of the capacitor.
To integrate logic and memory devices in a single chip configuration without degrading transistor performance, low-temperature MIM capacitors with Ta2O5 as a dielectric material are currently used in the semiconductor manufacturing arts. In conventional MIM capacitor manufacturing processes, the total number of additional lithography steps generally required to manufacture capacitors in the BEOL process is in the range of 2 to 3. In order to manufacture SoC memory devices, however, additional lithography steps may be required. Additional lithography steps, however, increase mask add-on costs. Thus, the present inventor has concluded that a need exists for a new process for manufacturing logic-based embedded DRAM, including MIM capacitors thereof, without increasing mask add-on costs as one or more back-end lithography steps are added.
The following summary of the invention is provided to facilitate an understanding of some of the innovative features unique to the present invention, and is not intended to be a full description. A full appreciation of the various aspects of the invention can be gained by taking the entire specification, claims, drawings, and abstract as a whole.
It is therefore one aspect of the present invention to provide an improved semiconductor fabrication method and system.
It is another aspect of the present invention to provide a method and system for fabricating a MIM capacitor.
It is yet another aspect of the present invention to provide a method and system for fabricating an MIM (metal insulator metal) capacitor utilized in an embedded DRAM-based semiconductor device.
The above and other aspects of the present invention are achieved as is now described. A method for forming a metal-interlayer-metal (MIM) device in an embedded memory device, including semiconductor devices thereof. An MIM device can be formed upon a semiconductor substrate utilizing no more than one additional photo mask layer prior to the implementation of a back-end-of-line (BEOL) semiconductor fabrication operation, such that the MIM device can be configured as a low temperature MIM device that is fully compatible with logical semiconductor devices, thereby reducing associated manufacturing costs. The MIM device may be configured as an MIM capacitor for logic-based embedded DRAM devices, resulting in a high capacitance performed via an effective area extension of DRAM cell capacitors. Additionally, a low-temperature MIM capacitor thereof may be readily integrated for both Cu (Copper) and AlCu (Aluminum Copper) BEOL fabrication processes.
Accordingly, in a first and preferred embodiment of the present invention, a MIM capacitor may be formed according to the following general fabrication process:
1. FEOL process to form the transistors (both LOGIC and DRAM), followed by the formation of a first inter-dielectric layer (ILD1).
2. Formation of SiON and second inter-dielectric layer (ILD2).
3. HAR contact formation.
4. Deposit SiON, perform DRAM crown lithography operation, followed by an oxide etch and a stop on SiON.
5. W (Tungsten) plug etch back.
6. TiN deposition and PR (or BARC) coating
7. PR and TiN etch back to form recess.
8. Deposit TA2O5 (or BST), TiN, and W
9. W/TiN/TA2O5 (or BST) etching back (or CMP) with a stop on SiON, followed by a removal of SiON
10. BEOL process of CU or AlCu
In a second and alternative preferred embodiment of the present invention, an MIM capacitor may be formed according to the following general fabrication process:
1. FEOL process to form transistors, followed by ILD, contact, and M1 formation.
2. IMD1 deposition and CMP, DRAM cell node photo and etch, followed by TiN formation.
3. PR (Photo Resist) coating
4. PR and TiN etching back to form recess in cell node followed by PR stripping operation.
5. TA2O5 (or BST) TiN, and W deposition.
6. W CMP (or etch back) with a stop on oxide.
7. VIA1 photo and etch and W-plug formation.
8. M2 (Metal-2) formation and subsequent standard BEOL process.